High Frequency PCB Knowledge: How to Minimize Insertion Loss and Reflection

As communication systems push into millimeter-wave frequencies and high-speed digital designs approach 10+Gbps data rates, signal degradation becomes the limiting factor in system performance. At these frequencies, a PCB trace is no longer a simple conductor—it's a transmission line where every geometry variation, material property, and manufacturing artifact affects Signal Integrity. Insertion loss and reflection, the two primary degradation mechanisms, determine whether your design performs reliably or fails catastrophically.

Understanding how to minimize these losses separates successful high-frequency designs from expensive prototypes that never meet specifications. This knowledge applies across applications from 5G base stations to Automotive Radar to high-speed data center interconnects.

Understanding Insertion Loss and Reflection

Before addressing mitigation strategies, it's essential to understand what causes signal degradation in high-frequency PCBs.

What Is Insertion Loss

Insertion loss represents the reduction in signal power as it travels through a transmission path. It's expressed in decibels (dB) and includes all losses between the input and output of the transmission line:

Total Insertion Loss = Conductor Losses + Dielectric Losses + Radiation Losses + Leakage Losses

Conductor losses arise from the finite conductivity of copper. At DC, this is simply I²R resistance. At high frequencies, Skin Effect forces current to flow in an increasingly thin layer near the conductor surface, dramatically increasing effective resistance. A 1mm wide trace at 1 GHz uses only about 21% of its cross-sectional area, effectively reducing width to approximately 0.21mm.

Dielectric losses occur as the alternating electric field in the transmission line causes molecular polarization in the substrate material. Energy dissipates as heat. Dielectric loss is characterized by the loss tangent (tan δ)—lower values indicate better performance. Standard Fr-4 has tan δ around 0.02 at GHz frequencies, while high-performance RF materials have tan δ below 0.005.

Radiation losses occur when the transmission line radiates energy. Microstrip traces radiate more than stripline, and radiation increases with frequency. Poor grounding and discontinuities amplify radiation losses.

Leakage losses through the dielectric are typically negligible at PCB frequencies but can matter at very high frequencies or for specialized materials.

What Is Reflection

Reflection occurs when a signal encounters impedance discontinuities along its path. The reflection coefficient (Γ) quantifies this:

Γ = (ZL - Z0) / (ZL + Z0)

Where ZL is the load impedance and Z0 is the Characteristic Impedance of the transmission line. When ZL equals Z0, reflection is zero. Any mismatch causes reflections that travel back toward the source, distorting the signal waveform.

Sources of reflection include:

• Trace width variations creating impedance changes
• Pad and component footprints with different impedance than the trace
• Vias with parasitic inductance and capacitance
• Connectors and transitions between board sections
• Impedance mismatches at signal source and load

Material Selection for Low Loss

Material choice fundamentally determines high-frequency performance. Making informed material selections early prevents problems that cannot be fixed during layout.

Dielectric Constant (Dk)

The Dielectric Constant affects impedance, wavelength, and coupling between traces. Key considerations:

• Consistency: Dk variation across the board and between batches affects impedance uniformity
• Temperature stability: Dk changes with temperature (Dk/Tg relationship). High-Tg materials maintain stable Dk across temperature ranges.
• Frequency dependence: Dk typically decreases at higher frequencies. Account for this when designing at mm-wave frequencies.
• XY variation: Woven glass reinforced materials have different Dk in the weave direction versus the fill direction. This anisotropy affects differential pair behavior.

Loss Tangent (Df)

Loss tangent directly determines dielectric loss at your operating frequency. Higher frequencies increase loss exponentially, making low-Df materials essential above 10 GHz:

• Standard Fr-4: Df ~0.02, suitable up to 3 GHz for short traces
• Mid-loss materials: Df ~0.01, suitable up to 10 GHz
• Low-loss materials: Df ~0.005, suitable up to 25 GHz
• Ultra-low-loss materials: Df ~0.002, suitable for mm-wave applications

Popular RF/Microwave Materials

Rogers RO4003C: Hydrocarbon ceramic filled, Dk 3.38, Df 0.0027 at 10 GHz. Excellent balance of electrical and mechanical properties. Lower cost than pure PTFE materials. Widely used for RF and microwave applications up to 20 GHz.

Rogers RT/duroid 5880: PTFE fiberglass, Dk 2.2, Df 0.0009 at 10 GHz. Exceptional loss performance but mechanically softer and more expensive. Preferred for applications below 77 GHz requiring minimum loss.

Isola I-Speed: Modified FR-4 with improved loss characteristics, Df ~0.006. Compatible with standard PCB processing, lower cost than Rogers materials. Good choice for applications to 15 GHz.

Megtron 6/7: Low-loss epoxy, Df ~0.002. Designed for high-speed digital applications, also suitable for RF. Compatible with standard processing.

Material Processing Considerations

Some materials have processing constraints:

• PTFE materials require special processing (plasma treatment, specialized etching) for reliable copper adhesion
• High-Dk materials may require adjusted trace geometries for the same impedance
• Some fillers are abrasive, accelerating drill and routing tool wear
• Shelf life and storage conditions affect some materials

Trace Geometry Optimization

Trace geometry directly determines impedance and loss. Optimizing geometry is one of the most effective ways to improve high-frequency performance.

Microstrip vs. Stripline vs. Grounded Coplanar

Microstrip: Trace on outer layer with ground plane beneath. Simple to manufacture but higher radiation losses and sensitivity to surface contamination. Suitable for frequencies to approximately 30 GHz with careful design.

Stripline: Trace between two ground planes. Lower radiation losses and better shielding. More complex manufacturing but provides consistent impedance and reduced sensitivity to surface effects. Preferred for very high frequencies or applications requiring minimal EMI.

Grounded Coplanar Waveguide (GCPW): Trace with ground planes on either side and below, all connected with vias. Combines benefits of microstrip and stripline. Excellent for mm-wave frequencies. The side grounds improve mechanical robustness and reduce radiation.

Width and Thickness Selection

For a given impedance target, trace width and dielectric thickness trade off:

• Wider traces: Lower current density, reduced conductor loss. But more susceptible to undesired coupling.
• Narrower traces: Higher current density, increased conductor loss. But more trace routing options.
• Thicker copper: Lower conductor loss at high frequencies. But affects impedance for given width.

For very high frequencies (above 20 GHz), consider ounce copper weights above standard 1oz. Heavier copper reduces Skin Effect resistance, but requires adjusted geometries for Impedance Control.

Impedance Tolerance

Manufacturing tolerances affect impedance accuracy. For high-frequency designs:

• Specify impedance tolerances tighter than ±10% when your design margin allows
• Account for worst-case impedance variation when calculating reflection and loss budgets
• Use impedance coupons on the panel to verify process capability
• Consider Dielectric Constant variation as well as trace width variation

Via Design for High Frequency

Vias introduce discontinuities that cause reflection and increase loss. Careful via design minimizes these effects.

Via Equivalent Circuit

A via has parasitic inductance and capacitance that create resonance effects:

• Via inductance: Typically 0.3-0.5 nH per mm of via length. Creates series impedance in the signal path.
• Via capacitance: Pads and antipads create capacitive coupling to reference planes. Creates shunt loading.
• Resonance: At frequencies where parasitic LC approaches resonance (typically 10-30 GHz for typical PCB vias), via impedance becomes very high, causing severe reflection.

Via Transition Design

Minimize via discontinuities through design:

• Via length: Use the thinnest board stackup compatible with your design. Shorter vias have lower inductance.
• Via diameter: Smaller holes have higher inductance. Use the largest practical hole size for via farms and return paths.
• Pad size: Minimize pad diameter. Larger pads increase capacitance to reference planes.
• Antipad clearance: Provide adequate clearance to reference planes. Larger antipads reduce parasitic capacitance.

Back-Drilling

Back-drilling removes the unused portion of through-hole vias, eliminating stub effects. For very high frequencies (above 20 GHz):

• The stub beyond the destination layer acts as an antenna and resonator
• Back-drill depth must be controlled precisely to avoid damaging the signal layer
• Use depth-control back-drilling for consistent results
• Verify back-drill removal with X-ray or cross-section analysis

Ground Via Placement

Ground vias adjacent to signal vias provide return paths:

• Place return vias within 2-3x the dielectric thickness of the signal layer
• For differential pairs, place return vias near each signal via or between the pair
• Use via chains rather than single vias for low inductance grounding
• Consider differential via design for minimal skew in high-speed differential pairs

Differential Pair Design

High-speed serial interfaces (56G/112G PAM4, PCIe 5/6, etc.) demand careful differential pair design to minimize skew and mode conversion.

Coupling and Spacing

Coupling coefficient affects differential impedance:

• Tight coupling: S = 1x trace width. Higher coupling reduces differential impedance, enables tighter spacing
• Loose coupling: S = 2-3x trace width. Easier manufacturing, lower cross-talk but requires more space
• Target impedance: Most interfaces target 100Ω differential ±10%. Adjust single-ended impedance and spacing to achieve this

Skew Management

Skew—difference in propagation delay between pair members—causes mode conversion from differential to common-mode signals:

• Length matching: Match pair lengths to within 0.05ps per inch for 56G+ PAM4. Tight tolerances require careful serpentine routing.
• Material symmetry: Use symmetrical stackup. Avoid situations where one trace has different dielectric thickness than the other.
• Via matching: Both traces should transition layers together with matched via lengths.

Differential Via Design

For differential pairs transitioning layers:

• Place both vias as close together as manufacturing allows
• Use differential via anti-pads in reference planes
• Compensate for via stub length with back-drilling if needed
• Consider pi or tee networks to match impedance through the via transition

Connector and Component Transitions

Every transition between different transmission structures creates discontinuity. Managing transitions carefully is essential for overall performance.

Connector Land Patterns

Connector footprints often create impedance discontinuities:

• Use connector land patterns designed for your board material and thickness
• Consider the effect of connector housing on electromagnetic fields
• Provide adequate thermal relief for solder connections without compromising RF performance
• Include provisions for flange mounting if mechanical stability is needed

Component Pad Effects

Component mounting pads create capacitance that lowers impedance at the pad:

• For passive components, use pads sized for the component and soldering requirements
• Consider stepped-Impedance Matching where pad size creates intentional discontinuity compensated by trace geometry
• Use 3D electromagnetic simulation to model pad effects at mm-wave frequencies

Launch Transitions

For board-edge launches to coaxial connectors:

• Design launches with 50Ω Impedance Matching to the connector interface
• Use quarter-wave transformers or tapered transitions for wideband matching
• Verify launch performance with TDR measurements
• Consider mounting connector flush with board surface to minimize discontinuity

Power Distribution Network Effects

At high frequencies, the power distribution network (PDN) affects Signal Integrity through multiple mechanisms.

PDN Impedance

Currents drawn by active components flow through the PDN. If PDN impedance is high, switching noise couples into signals:

• Design power and ground planes with minimum separation (2-4 mils) for capacitance
• Use decoupling capacitors sized for the frequency range of switching transients
• Place capacitors close to power pins with minimal loop inductance
• Consider PDN impedance profiling to verify performance at operating frequencies

Simultaneous Switching Noise

When multiple outputs switch simultaneously, PDN voltage droop can affect signal levels:

• Minimize loop area in power delivery paths
• Use solid reference planes adjacent to signal layers
• Consider on-board regulation to localize power switching transients

Design Verification and Simulation

High-frequency design requires verification beyond DC continuity testing.

Electromagnetic Simulation

For designs above 10 GHz, 3D electromagnetic simulation is essential:

• Model critical discontinuities: vias, bends, transitions
• Extract S-parameters for inclusion in system-level simulation
• Verify differential pair coupling and impedance
• Optimize geometry before manufacturing

Simulation accuracy depends on material model accuracy. Work with your material supplier for dielectric properties at your operating frequency.

Time Domain Reflectometry (TDR)

TDR measurements reveal impedance discontinuities:

• Use TDR to verify impedance uniformity of fabricated boards
• Identify problematic discontinuities for redesign or compensation
• Compare measured TDR with simulation predictions
• TDR can resolve discontinuities of approximately 5ps or longer

Vector Network Analysis (VNA)

VNA measurements characterize full transmission performance:

• S21 (insertion loss): Measure actual Signal Loss including conductor, dielectric, and radiation effects
• S11 (return loss): Quantify reflection at input, revealing impedance mismatches
• Differential measurements: For differential pairs, mixed-mode S-parameters characterize common-mode and differential mode behavior

Manufacturing Considerations

Impedance Control

Communicate impedance requirements clearly to your manufacturer:

• Specify target impedance and tolerance
• Identify impedance-critical traces requiring controlled geometry
• Request impedance test coupons for verification
• Provide stackup information including material properties

Surface Finish Effects

Surface finish affects high-frequency loss and bonding:

• ENIG (Electroless Nickel Immersion Gold): Widely used, but nickel layer has higher loss at very high frequencies. Consider ENEPIG for improved performance.
• Immersion silver: Good conductivity, but prone to tarnishing. Limited shelf life.
• OSP: Thin organic coating with minimal effect on impedance. But limited solderability and shelf life.
• Hard gold: Excellent durability for edge connectors or repeated mating. But expensive for entire boards.

Solder Mask and Overlays

Solder mask affects microstrip trace impedance:

• The mask adds dielectric thickness above the trace, lowering impedance
• For mm-wave designs, consider selective masking or liquid photoimageable (LPI) mask with known thickness
• Simulation should include mask dielectric properties if used

Loss Budget Allocation

Design to a total loss budget, allocating allowable loss to each segment:

• Connector losses: Typically 0.1-0.3 dB per connector pair
• Transmission line loss: Depends on material, geometry, and frequency. Budget based on material data and simulation.
• Via losses: Typically 0.1-0.5 dB per via depending on design
• Mismatch losses: Budget for return loss, typically allowing 10-15 dB return loss margin

Conclusion

Minimizing insertion loss and reflection in high-frequency PCBs requires attention to every design detail. From material selection through trace geometry, via design, and manufacturing communication, each decision affects final performance.

The key principles are straightforward: choose materials with appropriate loss characteristics, maintain consistent impedance through careful geometry control, minimize discontinuities from vias and transitions, and verify designs through simulation and measurement. But applying these principles requires expertise developed through experience and collaboration with materials suppliers, manufacturers, and measurement specialists.

As frequencies continue rising—toward 5G Millimeter Wave bands, Automotive Radar, and 200+Gbps data links—the techniques for loss minimization become even more critical. Designs that worked at 10 GHz fail at 30 GHz without careful attention to the principles outlined here. Investing in high-frequency expertise and simulation capabilities enables successful designs that meet performance requirements on the first spin.

Work closely with your Pcb Manufacturer throughout the design process. Their expertise in material handling, Controlled Impedance processing, and high-frequency fabrication complements your design capabilities. Early collaboration prevents costly redesigns and ensures that designed-for performance becomes manufactured reality.